A PGA is an indispensable RF frontend block to support wireless transceivers as shown in Fig.1. The input dynamic range which can provide a stable power level is determined by the PGA gain control range. The RF research is focusing on the high data-rate communication. Hence, the requirement of the PGA section is to support large bandwidth. Fig.2 shows the block diagram of the proposed circuit.

  It is desirable to possess enhanced characteristics like low power consumption, good input and output impedance matching to have the maximum power transfer, small die-footprint. To support low power applications, the supply voltage is reduced which limits the gain linearity performance. Hence, the proposed exponential current switching is introduced to maintain the gain linearity. To have a good impedance matching, a common-base amplifier with transimpedance load and a common-collector amplifier which are referred to as the input stage and output stage respectively are used. To have a small die-footprint and large bandwidth, Cherry-Hooper amplifiers are used to produce inductive peaking without using capacitors or inductors to produce zeros. Hence, the proposed PGA is more area efficient.

  DC offset is the most prevailing consequence of the process variation in differential circuits. There are many design methods to overcome the dc offset, and requirement for a low-loss, low-power, and compact dc offset cancellation (DCOC) is considered. Without additional dc power, the RC high-pass filter (RC-HPF) becomes apparent.

  In this report, a PGA used in a high data-rate transceiver based on long-battery-life, good linearity, low-cost is proposed. The sub-blocks of Two DVGAs as shown in Fig.3 and the post amplifier along with the wideband interconnect networks are analyzed. Fig.4 shows the micrograph of the proposed PGA, and Fig.5 shows the measurement setup for the proposed PGA.

Fig. 1

Fig. 2

Fig. 3

Fig. 4

Fig. 5


  I would like to express my deepest gratitude to all those who have made this project possible and also made it a rewarding and precious experience. First, I would like to thank my advisor, Professor Shuo-Hung Hsu, for his guidance and much assistance throughout my study in HSDIC lab this year. He gave me full scope to my abilities in developing my project. It has been a great privilege to be a part of his group. I am also indebted to the doctoral student, Ping-Yi Wang. His broad perspectives inspired me; without his enlightening instruction, I could not complete four ICs shown below,

1.A Current-Reused Transformer-Based Quadrature Voltage Control Oscillator in 0.18-μm CMOS technology.

2.A Quadrature Voltage Control Oscillator Using Eight-Shaped Transformer in 0.18-μm CMOS technology.

3.A Linear-in-decibel Programmable Gain Amplifier with Bandwidth Enhancement Techniques in SiGe 0.18-μm BiCMOS technology.

4.An OOK demodulation receiver in 90-nm CMOS technology.

  In addition, I would also like to thank all members in HSDIC group. They rescued me many times from the battles in countless hours with the layouts the simulation tools.

  In the past year, I learned how to use EM simulation tool “Sonnet” to design monolithic transformers, balun transformers and inductors; I utilized the circuit simulator, Spectre, to do simulations. I put a lot of effort into understanding the basic concepts of different circuits including voltage-controlled oscillators, quadrature voltage-controlled oscillators, digitally variable gain amplifiers, programmable gain amplifiers, and receivers. It is a really enriching experience throughout my study at NTHU, or even my life. To be an engineer, taking care of all details is imperative; the best way out is always through.